epyc 7473x firmware · threatengine.sh

Home/Product/amd epyc 7473x firmware

Product

amd epyc 7473x firmware

55 known vulnerabilities across versions

Vulnerabilities are listed by affected version. Select any CVE for the full briefing and its intelligence graph.

Sort Min CVSS Published since

< milanpi_1.0.0.b

Improper re-initialization of IOMMU during the DRTM event may permit an untrusted platform configuration to persist, allowing an a

< milanpi_1.0.0.b

IOMMU improperly handles certain special address ranges with invalid device table entries (DTEs), which may allow an attacker with

< milanpi_1.0.0.5

A TOCTOU (Time-Of-Check-Time-Of-Use) in SMM may allow an attacker with ring0 privileges and access to the BIOS menu or UEFI shell

< milanpi_1.0.0.5

An out of bounds memory write when processing the AMD PSP1 Configuration Block (APCB) could allow an attacker with access the abil

< milanpi_1.0.0.d

Improper restriction of write operations in SNP firmware could allow a malicious hypervisor to potentially overwrite a guest's mem

< milanpi_1.0.0.d

Improper input validation in SEV-SNP could allow a malicious hypervisor to read or overwrite guest memory potentially leading to d

< milanpi_1.0.0.d

Improper restriction of write operations in SNP firmware could allow a malicious hypervisor to overwrite a guest's UMC seed potent

< milanpi_1.0.0.c

Due to a code bug in Secure_TSC, SEV firmware may allow an attacker with high privileges to cause a guest to observe an incorrect

< milanpi_1.0.0.c

Failure to initialize memory in SEV Firmware may allow a privileged attacker to access stale data from other guests.

A privileged attacker can prevent delivery of debug exceptions to SEV-SNP guests potentially resulting in guests not receiving exp

< milanpi_1.0.0.c

Improper or unexpected behavior of the INVD instruction in some AMD CPUs may allow an attacker with a malicious hypervisor to affe

< milanpi_1.0.0.b

Improper address validation in ASP with SNP enabled may potentially allow an attacker to compromise guest memory integrity.

< milanpi_1.0.0.5

Insufficient DRAM address validation in System Management Unit (SMU) may allow an attacker to read/write from/to an invalid DRAM a

< milanpi_1.0.0.5

Insufficient input validation in the ASP Bootloader may enable a privileged attacker with physical access to expose the contents o

< milanpi_1.0.0.7

TOCTOU in the ASP Bootloader may allow an attacker with physical access to tamper with SPI ROM records after memory content verifi

< milanpi_1.0.0.a

SMM configuration may not be immutable, as intended, when SNP is enabled resulting in a potential limited loss of guest memory int

< milanpi_1.0.0.b

Insufficient DRAM address validation in System Management Unit (SMU) may allow an attacker to read/write from/to an invalid DRAM a

< milanpi_1.0.0.a

Failure to validate the value in APCB may allow a privileged attacker to tamper with the APCB token to force an out-of-bounds memo

< milanpi_1.0.0.c

A side channel vulnerability on some of the AMD CPUs may allow an attacker to influence the return address prediction. This may re

A potential power side-channel vulnerability in some AMD processors may allow an authenticated attacker to use the power reporting

Insufficient validation of inputs in SVC_MAP_USER_STACK in the ASP (AMD Secure Processor) bootloader may allow an attacker with a

An attacker with a compromised ASP could possibly send malformed commands to an ASP on another CPU, resulting in an out of bounds

Improper access control settings in ASP Bootloader may allow an attacker to corrupt the return address causing a stack-based buffe

Insufficient input validation on the model specific register: VM_HSAVE_PA may potentially lead to loss of SEV-SNP guest memory int

Improper input validation in ABL may enable an attacker with physical access, to perform arbitrary memory overwrites, potentially

Insufficient syscall input validation in the ASP Bootloader may allow a privileged attacker to execute arbitrary DMA copies, which

Improper validation of DRAM addresses in SMU may allow an attacker to overwrite sensitive memory locations within the ASP potentia

Insufficient input validation in the SMU may enable a privileged attacker to write beyond the intended bounds of a shared memory b

Insufficient input validation in the SMU may allow an attacker to corrupt SMU SRAM potentially leading to a loss of integrity or d

< milanpi_1.0.0.9

Insufficient address validation, may allow an attacker with a compromised ABL and UApp to corrupt sensitive memory locations poten

< milanpi_1.0.0.9

Insufficient input validation of mailbox data in the SMU may allow an attacker to coerce the SMU to corrupt SMRAM, potentially lea

< milanpi_1.0.0.6

A compromised or malicious ABL or UApp could send a SHA256 system call to the bootloader, which may result in exposure of ASP memo

< milanpi_1.0.0.6

A TOCTOU in ASP bootloader may allow an attacker to tamper with the SPI ROM following data read to memory potentially resulting in

< milanpi_1.0.0.6

Insufficient bounds checking in ASP may allow an attacker to issue a system call from a compromised ABL which may cause arbitrary

< milanpi-sp3_1.0.0.9

Improper input validation and bounds checking in SEV firmware may leak scratch buffer bytes leading to potential information discl

IBPB may not prevent return branch predictions from being specified by pre-IBPB branch targets leading to a potential information

Execution unit scheduler contention may lead to a side channel vulnerability found on AMD CPU microarchitectures codenamed “Zen

< milanpi-sp3_1.0.0.7

Improper validation of the BIOS directory may allow for searches to read beyond the directory table copy in RAM, exposing out of b

< milanpi-sp3_1.0.0.7

Insufficient bound checks in the System Management Unit (SMU) may result in access to an invalid address space that could result i

< milanpi-sp3_1.0.0.7

Insufficient checks in System Management Unit (SMU) FeatureConfig may result in reenabling features potentially resulting in denia

< milanpi-sp3_1.0.0.7

Insufficient General Purpose IO (GPIO) bounds check in System Management Unit (SMU) may result in access/updates from/to invalid a

< milanpi-sp3_1.0.0.7

Insufficient bound checks in the System Management Unit (SMU) may result in a system voltage malfunction that could result in deni

< milanpi-sp3_1.0.0.7

Insufficient bound checks related to PCIE in the System Management Unit (SMU) may result in access to an invalid address space tha

< milanpi-sp3_1.0.0.7

Insufficient bounds checking in an SMU mailbox register could allow an attacker to potentially read outside of the SRAM address ra

< milanpi-sp3_1.0.0.7

A TOCTOU race condition in SMU may allow for the caller to obtain and manipulate the address of a message port register which may

< milanpi-sp3_1.0.0.7

Failure to assign a new report ID to an imported guest may potentially result in an SEV-SNP guest VM being tricked into trusting a

< milanpi-sp3_1.0.0.7

Failure to flush the Translation Lookaside Buffer (TLB) of the I/O memory management unit (IOMMU) may lead an IO device to write t

< milanpi-sp3_1.0.0.7

Failure to validate the integer operand in ASP (AMD Secure Processor) bootloader may allow an attacker to introduce an integer ove

< milanpi-sp3_1.0.0.7

In SEV guest VMs, the CPU may fail to flush the Translation Lookaside Buffer (TLB) following a particular sequence of operations t

< milanpi-sp3_1.0.0.7

A bug in AMD CPU’s core logic may allow for an attacker, using specific code from an unprivileged VM, to trigger a CPU core hang

< milanpi-sp3_1.0.0.4

Insufficient validation of addresses in AMD Secure Processor (ASP) firmware system call may potentially lead to arbitrary code exe

< milanpi-sp3_1.0.0.4

Improper validation of destination address in SVC_LOAD_FW_IMAGE_BY_INSTANCE and SVC_LOAD_BINARY_BY_ATTRIB in a malicious UApp or A

< milanpi-sp3_1.0.0.4

Failure to validate inputs in SMM may allow an attacker to create a mishandled error leaving the DRTM UApp in a partially initiali

< milanpi-sp3_1.0.0.4

Failure to verify SEV-ES TMR is not in MMIO space, SEV-ES FW could result in a potential loss of integrity or availability.

< milanpi-sp3_1.0.0.4

A bug with the SEV-ES TMR may lead to a potential loss of memory integrity for SNP-active VMs.

Vulnerabilities
CISA KEV catalog
CWE weaknesses
CAPEC attack patterns
Package vulnerabilities

Threat intelligence
Threat actors
Tools & malware
ATT&CK techniques
IOCs

Detection & defense
Sigma rules
YARA rules
Atomic Red Team tests
D3FEND countermeasures

Compliance
NIST 800-53
ISO 27001:2022
SOC 2 TSC
PCI-DSS v4.0
CIS Controls v8.1

About
All capabilities
Live statistics
Data sources
Privacy policy
Terms of service

threatengine.sh · Open-source threat intelligence platform · 100+ authoritative sources · Every fact traces to its origin