When SMT is enabled, certain AMD processors may speculatively execute instructions using a target from the sibling thread after an

IBPB may not prevent return branch predictions from being specified by pre-IBPB branch targets leading to a potential information

Aliases in the branch predictor may cause some AMD processors to predict the wrong branch type potentially leading to information

Mis-trained branch predictions for return instructions may allow arbitrary speculative code execution under certain microarchitect

A potential vulnerability in some AMD processors using frequency scaling may allow an authenticated attacker to execute a timing a

LFENCE/JMP (mitigation V2-2) may not sufficiently mitigate CVE-2017-5715 on some AMD CPUs.

Some AMD CPUs may transiently execute beyond unconditional direct branches, which may potentially result in data leakage.