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amd athlon silver 3050u firmware

19 known vulnerabilities across versions

Vulnerabilities are listed by affected version. Select any CVE for the full briefing and its intelligence graph.

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< picassopi-fp5_1.0.0.e

Improper bounds checking in APCB firmware may allow an attacker to perform an out of bounds write, corrupting the APCB entry, pote

< picassopi-fp5_1.0.0.e

A malicious attacker in x86 can misconfigure the Trusted Memory Regions (TMRs), which may allow the attacker to set an arbitrary a

An attacker with specialized hardware and physical access to an impacted device may be able to perform a voltage fault injection a

< picassopi-fp5_1.0.0.f

Insufficient input validation in CpmDisplayFeatureSmm may allow an attacker to corrupt SMM memory by overwriting an arbitrary bit

Insufficient control flow management in AmdCpmGpioInitSmm may allow a privileged attacker to tamper with the SMM handler potential

Insufficient control flow management in AmdCpmOemSmm may allow a privileged attacker to tamper with the SMM handler potentially le

When SMT is enabled, certain AMD processors may speculatively execute instructions using a target from the sibling thread after an

Failure to validate the communication buffer and communication service in the BIOS may allow an attacker to tamper with the buffer

IBPB may not prevent return branch predictions from being specified by pre-IBPB branch targets leading to a potential information

Insufficient memory cleanup in the AMD Secure Processor (ASP) Trusted Execution Environment (TEE) may allow an authenticated attac

Insufficient verification of missing size check in 'LoadModule' may lead to an out-of-bounds write potentially allowing an attacke

Improper parameters handling in the AMD Secure Processor (ASP) kernel may allow a privileged attacker to elevate their privileges

Improper parameters handling in AMD Secure Processor (ASP) drivers may allow a privileged attacker to elevate their privileges pot

Aliases in the branch predictor may cause some AMD processors to predict the wrong branch type potentially leading to information

A malformed SMI (System Management Interface) command may allow an attacker to establish a corrupted SMI Trigger Info data structu

Mis-trained branch predictions for return instructions may allow arbitrary speculative code execution under certain microarchitect

A potential vulnerability in some AMD processors using frequency scaling may allow an authenticated attacker to execute a timing a

LFENCE/JMP (mitigation V2-2) may not sufficiently mitigate CVE-2017-5715 on some AMD CPUs.

Some AMD CPUs may transiently execute beyond unconditional direct branches, which may potentially result in data leakage.

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