Home/CVE/A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exce
CVE

CVE-2025-63384

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exce

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.

MEDIUM · CVSS 6.5 EPSS 0.00041
Schedule remediation
  • Public exploit or PoC is available
Sigma rules0 YARA rules0
⬡

Weakness Classification

CWE-266Incorrect Privilege Assignment
▤

Affected Products & Versions

1
chipsalliance rocketchip<= 1.6
⚠

Public Exploits & PoCs

1
pocgithub.com · RISC-V-Vulnerability-Disclosure_SRETgithub.com
▣

Scoring & Timeline

6.5
MEDIUM · CVSS v3.1 · cve@mitre.org
View on NVD
Attack Vector
Network Adjacent Local Physical
Attack Complexity
Low High
Privileges Required
None Low High
User Interaction
None Required
Scope
Unchanged Changed
Confidentiality
None Low High
Integrity
None Low High
Availability
None Low High
Published to NVD10 Nov 2025 · 08:15 PM
CVSS VectorCVSS:3.1/AV:N/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N
SSVC triage · cisa-vulnrichment
Exploitation
none
Automatable
no
Technical impact
total
SSVC asks the questions that actually drive patch urgency: is it being exploited, can attacks be automated, and how total is the impact.
🔗

References & Sources

1
Source URLs (vendor pages, mailing lists, write-ups). Exploit/PoC links are in their own section above to avoid duplication.
https://github.com/chipsalliance/rocket-chip.gitProduct
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