Home/CVE/Improper conditions check in some Intel(R) Xeon(R) processor memory controller configurations when using Intel(R) SGX ma
CVE

CVE-2024-23918

Improper conditions check in some Intel(R) Xeon(R) processor memory controller configurations when using Intel(R) SGX ma

Improper conditions check in some Intel(R) Xeon(R) processor memory controller configurations when using Intel(R) SGX may allow a privileged user to potentially enable escalation of privilege via local access.

HIGH · CVSS 8.8 EPSS 0.0007
Schedule remediation
  • CVSS base score ≥ 7.0
Sigma rules0 YARA rules0
⬡

Weakness Classification

CWE-92DEPRECATED: Improper Sanitization of Custom Special Characters
▣

Scoring & Timeline

8.8
HIGH · CVSS v3.1 · secure@intel.com
View on NVD
Attack Vector
Network Adjacent Local Physical
Attack Complexity
Low High
Privileges Required
None Low High
User Interaction
None Required
Scope
Unchanged Changed
Confidentiality
None Low High
Integrity
None Low High
Availability
None Low High
Published to NVD13 Nov 2024 · 09:15 PM
CVSS VectorCVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:H
SSVC triage · cisa-vulnrichment
Exploitation
none
Automatable
no
Technical impact
total
SSVC asks the questions that actually drive patch urgency: is it being exploited, can attacks be automated, and how total is the impact.
⚑

Vendor Advisories

7
suse-csafSUSE-SU-2025:20286-1
suse-csafSUSE-SU-2025:1032-1
suse-csafSUSE-SU-2025:20092-1
usnUSN-7149-1
suse-csafSUSE-SU-2024:4053-1
🔗

References & Sources

2
Source URLs (vendor pages, mailing lists, write-ups). Exploit/PoC links are in their own section above to avoid duplication.
https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01079.html
https://lists.debian.org/debian-lts-announce/2024/12/msg00024.html
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