Home/CVE/Debug message containing addresses of memory transactions in some Intel(R) 10th Generation Core Processors supporting SG
CVE

CVE-2020-24491

Debug message containing addresses of memory transactions in some Intel(R) 10th Generation Core Processors supporting SG

Debug message containing addresses of memory transactions in some Intel(R) 10th Generation Core Processors supporting SGX may allow a privileged user to potentially enable information disclosure via local access.

MEDIUM · CVSS 4.4 EPSS 0.00065
Monitor
  • No active-exploitation, high-EPSS, or public-exploit signals - routine patching cadence
Sigma rules0 YARA rules0
⬡

Weakness Classification

CWE-20Improper Input Validation
▤

Affected Products & Versions

3
intel core i3all versions
intel core i5all versions
intel core i7all versions
▣

Scoring & Timeline

4.4
MEDIUM · CVSS v3.1 · secure@intel.com
View on NVD
Attack Vector
Network Adjacent Local Physical
Attack Complexity
Low High
Privileges Required
None Low High
User Interaction
None Required
Scope
Unchanged Changed
Confidentiality
None Low High
Integrity
None Low High
Availability
None Low High
Published to NVD17 Feb 2021 · 02:15 PM
CVSS VectorCVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:U/C:H/I:N/A:N
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References & Sources

1
Source URLs (vendor pages, mailing lists, write-ups). Exploit/PoC links are in their own section above to avoid duplication.
https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00455.htmlPatchVendor Advisory
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