Home/CAPEC/Exploitation of Transient Instruction Execution
Attack Pattern

Exploitation of Transient Instruction Execution

CAPEC-663 · Standard · Stable
An adversary exploits a hardware design flaw in a CPU implementation of transient instruction execution to expose sensitive data and bypass/subvert access control over restricted resources. Typically, the adversary conducts a covert channel attack to target non-discarded microarchitectural changes caused by transient executions such as speculative execution, branch prediction, instruction pipelining, and/or out-of-order execution. The transient execution results in a series of instructions (gadgets) which construct covert channel and access/transfer the secret data.
likelihood: Low severity: Very High

Targets These Weaknesses (CWE)

3
The underlying weaknesses this attack pattern exploits. Follow into a CWE to see affected CVEs and its relationship tree.
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